1. Field of the Invention
This invention relates generally to wafer-level chip scale packages, and more particularly to forming a moat-like structure in a semiconductor wafer to restrict flow of a liquid prior to solidification of the liquid.
2. Description of the Related Art
A wafer-level chip scale package (CSP) is a package for an integrated circuit that is substantially the size of the integrated circuit or of a flip chip, which uses a wafer-level processing technique. Unlike a flip chip, the wafer-level CSP has one or more passivation layers on the active side of the die. Each passivation layer typically comprises a layer of photo-imageable polymer film. The wafer-level CSP is smaller than a standard ball grid array (BGA), typically uses metal traces of a re-distribution layer (RDL) to route solder ball pads to standard pitches, and uses CSP-size solder balls on the re-routed pads. A wafer-level CSP uses a standard surface mount technology assembly process that is also used for BGAs, and does not require underfill.
The use of a polymer collar around a solder ball, or solder bump, to support the solder ball in a wafer-level CSP is well known. When a semiconductor wafer, or wafer, is heated to the reflow temperature of the solder ball, some of the polymer collar material, which is very viscous at room temperature, becomes much less viscous, or liquefies. At times, the liquefied polymer collar material will disadvantageously flow farther from the solder ball than is desirable; occasionally merging with polymer collar material from an adjacent solder ball pad. Also, a solder ball disadvantageously tends to float on the liquefied polymer collar material. A solder ball will sometimes float to an adjacent solder ball pad, thereby creating a short. At times, a larger polymer collar is useful, but cannot be implemented with prior art wafer-level CSPs because a larger polymer collar would disadvantageously allow more liquefied polymer collar material to flow away from the polymer collar, thereby resulting in an undesirable appearance.
U.S. Pat. No. 6,437,434 entitled SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING INTERCONNECTION BOARD, issued Aug. 20, 2002 to Sugizaki, discloses an interconnection board that has a moat etched in silicon around a BGA pad in order to release the BGA pad from stress. The moat is purposefully pre-filled with an elastomer. However, Sugizaki does not disclose a moat formed in a photo-imageable polymer film, does not disclose a moat on an integrated circuit, and does not disclose any means for stopping the spread of polymer collar material.